// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hiddrphy_dx_static_reg_0_c_union_define.h
// Project line  :  IP
// Department    :  
// Author        :  Jason, Edward
// Version       :  .1
// Date          :  2011/11/29
// Description   :  The DDR PHY Controller Block
// Others        :  Generated automatically by nManager V4.2 
// History       :  Jason, Edward 2018/03/19 12:28:10 Create file
// ******************************************************************************

#ifndef __HIDDRPHY_DX_STATIC_REG_0_C_UNION_DEFINE_H__
#define __HIDDRPHY_DX_STATIC_REG_0_C_UNION_DEFINE_H__

/* Define the union U_DX_DXPHYCTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_0                     : 10  ; /* [31:22] */
        unsigned int    dxctl_tdc_offset_code_h   : 5  ; /* [21:17] */
        unsigned int    dxctl_tdc_offset_code_v   : 5  ; /* [16:12] */
        unsigned int    dxctl_pll_lt              : 2  ; /* [11:10] */
        unsigned int    dxctl_margin_cal_rank0_en : 1  ; /* [9] */
        unsigned int    dxctl_pll_sp              : 2  ; /* [8:7] */
        unsigned int    dxctl_pll_cpi             : 3  ; /* [6:4] */
        unsigned int    dxctl_pll_init            : 1  ; /* [3] */
        unsigned int    dxctl_pll_testen          : 1  ; /* [2] */
        unsigned int    rsv_1                     : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXPHYCTRL;

/* Define the union U_DX_IOCTL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dqs_ioctl_odtsel     : 3  ; /* [31:29] */
        unsigned int    dx_ioctl_odtsel      : 3  ; /* [28:26] */
        unsigned int    rsv_2                : 18  ; /* [25:8] */
        unsigned int    dxctl_ioctl_pe       : 2  ; /* [7:6] */
        unsigned int    dxctl_ioctl_hs       : 2  ; /* [5:4] */
        unsigned int    rsv_3                : 1  ; /* [3] */
        unsigned int    top_ioctl_odt_oe     : 1  ; /* [2] */
        unsigned int    dxctl_ioctl_dxiopldn : 1  ; /* [1] */
        unsigned int    rsv_4                : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_IOCTL;

/* Define the union U_DX_DQSSEL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_5                        : 8  ; /* [31:24] */
        unsigned int    reg_dbg_byt0_evntmt_dq47_sel : 1  ; /* [23] */
        unsigned int    rsv_6                        : 5  ; /* [22:18] */
        unsigned int    dxctl_dmswap_sel             : 2  ; /* [17:16] */
        unsigned int    dxctl_dqswap_sel             : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DQSSEL;

/* Define the union U_DX_DXNCKCTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_7               : 8  ; /* [31:24] */
        unsigned int    dxctl_rg_ck12p      : 4  ; /* [23:20] */
        unsigned int    dxctl_regcm2        : 4  ; /* [19:16] */
        unsigned int    dxctl_ck11p_dramclk : 4  ; /* [15:12] */
        unsigned int    dxctl_ck10p_cmd2t   : 3  ; /* [11:9] */
        unsigned int    dxctl_ck9p_cmd1t    : 5  ; /* [8:4] */
        unsigned int    dxctl_ck0p_mclk     : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXNCKCTRL;

/* Define the union U_DX_PHYPLLCTRL_DX */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dxctl_pll_lock : 1  ; /* [31] */
        unsigned int    rsv_8          : 25  ; /* [30:6] */
        unsigned int    dxctl_pll_test : 6  ; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_PHYPLLCTRL_DX;

/* Define the union U_DX_PHYCTRL2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dxctl_rx_ppfifo_ptr_en      : 1  ; /* [31] */
        unsigned int    wfifo_dxctl_passthrough     : 1  ; /* [30] */
        unsigned int    wfifo_dxctl_gcken           : 1  ; /* [29] */
        unsigned int    dxctl_reg_phy_wdata_ranksw  : 3  ; /* [28:26] */
        unsigned int    dxctl_ppfifo_ptr_en         : 1  ; /* [25] */
        unsigned int    dxctl_reg_rdffsel_2rank_en  : 1  ; /* [24] */
        unsigned int    dxctl_reg_wfifo_mode        : 1  ; /* [23] */
        unsigned int    rsv_9                       : 2  ; /* [22:21] */
        unsigned int    margin_cal_gate_en          : 1  ; /* [20] */
        unsigned int    dxctl_reg_sel_pos_rx        : 1  ; /* [19] */
        unsigned int    phy_type                    : 2  ; /* [18:17] */
        unsigned int    lpddr4_mode                 : 1  ; /* [16] */
        unsigned int    reg_evntmt_en_cmd           : 1  ; /* [15] */
        unsigned int    reg_evntmt_sel_cnt_cmd      : 1  ; /* [14] */
        unsigned int    reg_evntmt_sel_regread_cmd  : 1  ; /* [13] */
        unsigned int    reg_evntmt_tstmode_cmd      : 1  ; /* [12] */
        unsigned int    reg_evntmt_edin_dq47_sel    : 3  ; /* [11:9] */
        unsigned int    reg_evntmt_edin_dq03_sel    : 3  ; /* [8:6] */
        unsigned int    dxctl_reg_dvalid_selfgen_en : 1  ; /* [5] */
        unsigned int    ut_mode                     : 1  ; /* [4] */
        unsigned int    reg_hs_phy_debug_ck_duty    : 1  ; /* [3] */
        unsigned int    rsv_10                      : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_PHYCTRL2;

/* Define the union U_DX_IOCTL1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dxctl_ioctl_odt_iopldn      : 1  ; /* [31] */
        unsigned int    dxctl_odt_ioctl_ronsel      : 3  ; /* [30:28] */
        unsigned int    rsv_11                      : 2  ; /* [27:26] */
        unsigned int    dxctl_ioctl_squeach_pd      : 2  ; /* [25:24] */
        unsigned int    rsv_12                      : 10  ; /* [23:14] */
        unsigned int    dxctl_ioctl_genvref_pd      : 2  ; /* [13:12] */
        unsigned int    dxctl_odt_ioctl_rdsel_n     : 3  ; /* [11:9] */
        unsigned int    dxctl_odt_ioctl_rdsel_p     : 3  ; /* [8:6] */
        unsigned int    rsv_13                      : 4  ; /* [5:2] */
        unsigned int    dxctl_ioctl_genvref_range_2 : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_IOCTL1;

/* Define the union U_DX_IOCTL2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    ioctl_dq_rx_mode1            : 1  ; /* [31] */
        unsigned int    ioctl_dq_rx_mode0            : 1  ; /* [30] */
        unsigned int    rsv_14                       : 2  ; /* [29:28] */
        unsigned int    dq_vref_sel0                 : 1  ; /* [27] */
        unsigned int    dq_vref_sel1                 : 1  ; /* [26] */
        unsigned int    dxctl_ioctl_genvref_refsel_2 : 2  ; /* [25:24] */
        unsigned int    rsv_15                       : 4  ; /* [23:20] */
        unsigned int    dxctl_ioctl_genvref_refsel_1 : 2  ; /* [19:18] */
        unsigned int    rsv_16                       : 4  ; /* [17:14] */
        unsigned int    dxctl_ioctl_genvref_refsel_0 : 2  ; /* [13:12] */
        unsigned int    rsv_17                       : 4  ; /* [11:8] */
        unsigned int    dxctl_ioctl_genvref_range_1  : 2  ; /* [7:6] */
        unsigned int    rsv_18                       : 4  ; /* [5:2] */
        unsigned int    dxctl_ioctl_genvref_range_0  : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_IOCTL2;

/* Define the union U_DX_PHYPLLCTRL_DX2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_19                 : 15  ; /* [31:17] */
        unsigned int    dxctl_pll_lockin       : 1  ; /* [16] */
        unsigned int    rsv_20                 : 1  ; /* [15] */
        unsigned int    dxctl__pll_fopetestref : 1  ; /* [14] */
        unsigned int    rsv_21                 : 1  ; /* [13] */
        unsigned int    dxctl__pll_fopetestfb  : 1  ; /* [12] */
        unsigned int    rsv_22                 : 1  ; /* [11] */
        unsigned int    dxctl__pll_lockt_sel   : 1  ; /* [10] */
        unsigned int    rsv_23                 : 1  ; /* [9] */
        unsigned int    dxctl__pll_initsel     : 1  ; /* [8] */
        unsigned int    rsv_24                 : 1  ; /* [7] */
        unsigned int    dxctl__pll_en_cal      : 1  ; /* [6] */
        unsigned int    rsv_25                 : 1  ; /* [5] */
        unsigned int    dxctl__pll_enphsel     : 1  ; /* [4] */
        unsigned int    rsv_26                 : 1  ; /* [3] */
        unsigned int    dxctl__pll_bp_refvco   : 1  ; /* [2] */
        unsigned int    rsv_27                 : 1  ; /* [1] */
        unsigned int    dxctl__pll_bp_refpfd   : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_PHYPLLCTRL_DX2;

/* Define the union U_DX_PHYPLLCTRL_DX3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dxctl_phazmeter_status : 16  ; /* [31:16] */
        unsigned int    dxctl_phazmeter_in     : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_PHYPLLCTRL_DX3;

/* Define the union U_DX_IOCTL6 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dummy_ioctl_ronselp : 3  ; /* [31:29] */
        unsigned int    dummy_ioctl_ronseln : 3  ; /* [28:26] */
        unsigned int    dqs_ioctl_ronbselp  : 3  ; /* [25:23] */
        unsigned int    dqs_ioctl_ronbseln  : 3  ; /* [22:20] */
        unsigned int    dx_ioctl_pre_em     : 2  ; /* [19:18] */
        unsigned int    dx_ioctl_lp4x_en    : 2  ; /* [17:16] */
        unsigned int    dqs_ioctl_pre_em    : 2  ; /* [15:14] */
        unsigned int    dqs_ioctl_lp4x_en   : 2  ; /* [13:12] */
        unsigned int    dx_ioctl_ronseln    : 3  ; /* [11:9] */
        unsigned int    dx_ioctl_ronselp    : 3  ; /* [8:6] */
        unsigned int    dqs_ioctl_ronseln   : 3  ; /* [5:3] */
        unsigned int    dqs_ioctl_ronselp   : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_IOCTL6;

/* Define the union U_DX_DXNCLKBDL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_28           : 12  ; /* [31:20] */
        unsigned int    dxctl_refclk_bdl : 4  ; /* [19:16] */
        unsigned int    rsv_29           : 12  ; /* [15:4] */
        unsigned int    dxctl_fbclk_bdl  : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXNCLKBDL;

/* Define the union U_DX_DXNDCC5 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_30               : 11  ; /* [31:21] */
        unsigned int    dxctl_reg_tx_dcc_dqs : 7  ; /* [20:14] */
        unsigned int    dxctl_reg_tx_dcc_dm  : 7  ; /* [13:7] */
        unsigned int    dxctl_reg_rx_dcc_dm  : 7  ; /* [6:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXNDCC5;

/* Define the union U_DX_PHYCTRL0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_hs_phy_debug_duty           : 1  ; /* [31] */
        unsigned int    reg_hs_phy_debug                : 1  ; /* [30] */
        unsigned int    reg_sel_dqsgated_la_2nd_dqs     : 1  ; /* [29] */
        unsigned int    reg_rxmargin_inc_en_dqs         : 1  ; /* [28] */
        unsigned int    reg_rxmargin_dec_en_dqs         : 1  ; /* [27] */
        unsigned int    reg_rdqm_en_dqs                 : 1  ; /* [26] */
        unsigned int    reg_margin_2rank_en_dqs         : 1  ; /* [25] */
        unsigned int    reg_wdqsbdl_2rank_en_dqs        : 1  ; /* [24] */
        unsigned int    reg_tdvalid_vle_dqs             : 1  ; /* [23] */
        unsigned int    reg_tdvalid_manctl_dqs          : 1  ; /* [22] */
        unsigned int    reg_wrank_src_sel_dqs           : 2  ; /* [21:20] */
        unsigned int    reg_gatederr_chk_dis_2nd_dqs    : 1  ; /* [19] */
        unsigned int    reg_gatedla_pasthr_2nd_dqs      : 1  ; /* [18] */
        unsigned int    reg_tx_dqs_dcc_rank1_dqs        : 7  ; /* [17:11] */
        unsigned int    reg_lvdqsclk_rank1_sel_dqs      : 1  ; /* [10] */
        unsigned int    dxctl_sync_ppfifo_ptr           : 1  ; /* [9] */
        unsigned int    reg_evntmt_sel_regread_dq03_dqs : 1  ; /* [8] */
        unsigned int    reg_evntmt_sel_regread_dq47_dqs : 1  ; /* [7] */
        unsigned int    reg_evntmt_regread_dbgen_dqs    : 1  ; /* [6] */
        unsigned int    reg_wdqsrank0_pre1t_sel_dqs     : 1  ; /* [5] */
        unsigned int    reg_wdqsrank1_pre1t_sel_dqs     : 1  ; /* [4] */
        unsigned int    reg_rx_trans_1rken_dqs          : 1  ; /* [3] */
        unsigned int    reg_evntmt_en_dqs               : 1  ; /* [2] */
        unsigned int    reg_evntmt_sel_cnt_dqs          : 1  ; /* [1] */
        unsigned int    reg_evntmt_tstmode_dqs          : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_PHYCTRL0;

/* Define the union U_DX_DXNMISCCTRL0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_reserve_dq0dten_dqs      : 1  ; /* [31] */
        unsigned int    dxctl_reg_rxfifo_r1t_sel_dqs : 1  ; /* [30] */
        unsigned int    dxctl_reg_dqsg_extend_2t_dqs : 1  ; /* [29] */
        unsigned int    dxctl_reg_dqsg_extend_en_dqs : 1  ; /* [28] */
        unsigned int    dxctl_reg_dqsg_toggle_en     : 1  ; /* [27] */
        unsigned int    dxctl_ptrgated_en            : 1  ; /* [26] */
        unsigned int    dxctl_reg_wpst_1p5ten        : 1  ; /* [25] */
        unsigned int    dxctl_reg_sel_lvdqsclkdiv2   : 1  ; /* [24] */
        unsigned int    dxctl_bufphyclkdiv2          : 1  ; /* [23] */
        unsigned int    dxctl_lvdqclkdiv2            : 1  ; /* [22] */
        unsigned int    dxctl_dqsgatedla             : 1  ; /* [21] */
        unsigned int    dxctl_rxp_2nd_dm             : 1  ; /* [20] */
        unsigned int    dxctl_rxn_2nd_dm             : 1  ; /* [19] */
        unsigned int    dxctl_dqs_h                  : 1  ; /* [18] */
        unsigned int    dxctl_dqs_l                  : 1  ; /* [17] */
        unsigned int    reg_dqsdly_pri_en            : 1  ; /* [16] */
        unsigned int    dxctl_rxp_2nd_dq             : 8  ; /* [15:8] */
        unsigned int    dxctl_rxn_2nd_dq             : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXNMISCCTRL0;

/* Define the union U_DX_IOCTL7 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_31                : 2  ; /* [31:30] */
        unsigned int    dummy_ioctl_ronbseln  : 3  ; /* [29:27] */
        unsigned int    dummy_ioctl_ronbselp  : 3  ; /* [26:24] */
        unsigned int    dm_ioctl_tx_duty_en   : 2  ; /* [23:22] */
        unsigned int    dm_ioctl_rx_duty_en   : 2  ; /* [21:20] */
        unsigned int    dm_ioctl_tx_duty_inc  : 2  ; /* [19:18] */
        unsigned int    dm_ioctl_rx_duty_inc  : 2  ; /* [17:16] */
        unsigned int    dm_ioctl_tx_duty_sel  : 2  ; /* [15:14] */
        unsigned int    dm_ioctl_rx_duty_sel  : 2  ; /* [13:12] */
        unsigned int    dqs_ioctl_tx_duty_en  : 2  ; /* [11:10] */
        unsigned int    dqs_ioctl_rx_duty_en  : 2  ; /* [9:8] */
        unsigned int    dqs_ioctl_tx_duty_inc : 2  ; /* [7:6] */
        unsigned int    dqs_ioctl_rx_duty_inc : 2  ; /* [5:4] */
        unsigned int    dqs_ioctl_tx_duty_sel : 2  ; /* [3:2] */
        unsigned int    dqs_ioctl_rx_duty_sel : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_IOCTL7;

/* Define the union U_DX_DXNMISCCTRL1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_dqsoe_by_ie_dqs   : 1  ; /* [31] */
        unsigned int    reg_dqsoe_by_wren_dqs : 1  ; /* [30] */
        unsigned int    dxctl_dqclk1x         : 3  ; /* [29:27] */
        unsigned int    dxctl_dqclk2x         : 3  ; /* [26:24] */
        unsigned int    dxctl_dqclk1x_rank1   : 3  ; /* [23:21] */
        unsigned int    dxctl_dqclk2x_rank1   : 3  ; /* [20:18] */
        unsigned int    dxctl_dqsgclk1x       : 3  ; /* [17:15] */
        unsigned int    dxctl_dqsgclk2x       : 3  ; /* [14:12] */
        unsigned int    dxctl_dqsclk1x        : 3  ; /* [11:9] */
        unsigned int    dxctl_dqsclk2x        : 3  ; /* [8:6] */
        unsigned int    dxctl_mclk1x          : 3  ; /* [5:3] */
        unsigned int    dxctl_mclk2x          : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXNMISCCTRL1;

/* Define the union U_DX_DXDEBUG0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_32                           : 4  ; /* [31:28] */
        unsigned int    dxctl_evntmt_result_dqm2dq7_byt  : 1  ; /* [27] */
        unsigned int    dxctl_evntmt_result_dqs02dq3_byt : 1  ; /* [26] */
        unsigned int    dxctl_evntmt_done_dqm2dq7_byt    : 1  ; /* [25] */
        unsigned int    dxctl_evntmt_done_dqs02dq3_byt   : 1  ; /* [24] */
        unsigned int    dxctl_rlresult_gds_dqs           : 8  ; /* [23:16] */
        unsigned int    dxdbg_dqs_s0a                    : 1  ; /* [15] */
        unsigned int    dxdbg_dqs_s0b                    : 1  ; /* [14] */
        unsigned int    dxdbg_dqs_s1a                    : 1  ; /* [13] */
        unsigned int    dxdbg_dqs_s1b                    : 1  ; /* [12] */
        unsigned int    dxdbg_dqs_s2a                    : 1  ; /* [11] */
        unsigned int    dxdbg_dqs_s2b                    : 1  ; /* [10] */
        unsigned int    dxdbg_dqs_rdcnt                  : 4  ; /* [9:6] */
        unsigned int    dxdbg_dqs_ca                     : 3  ; /* [5:3] */
        unsigned int    dxdbg_dqs_cb                     : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXDEBUG0;

/* Define the union U_DX_DXPHYRSVD */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_33         : 16  ; /* [31:16] */
        unsigned int    dxctl_rsvdctrl : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXPHYRSVD;

/* Define the union U_DX_DXNMISCCTRL2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dxctl_dqsclk1x_rank1             : 3  ; /* [31:29] */
        unsigned int    dxctl_reg_post_gateden           : 1  ; /* [28] */
        unsigned int    dxctl_byp_clk_gated_dis          : 1  ; /* [27] */
        unsigned int    dxctl_dqsclk2x_rank1             : 3  ; /* [26:24] */
        unsigned int    dxctl_reg_sel_combout            : 1  ; /* [23] */
        unsigned int    dxctl_reg_tspc_sel               : 1  ; /* [22] */
        unsigned int    dxctl_reset_n_phyupdate_req      : 1  ; /* [21] */
        unsigned int    dxctl_reg_pn_dlyen               : 1  ; /* [20] */
        unsigned int    dxctl_reg_pre_margin_gated_0     : 1  ; /* [19] */
        unsigned int    dxctl_reg_pre_margin_gated_1     : 1  ; /* [18] */
        unsigned int    dxctl_reg_post_margin_gated_0    : 1  ; /* [17] */
        unsigned int    dxctl_reg_post_margin_gated_1    : 1  ; /* [16] */
        unsigned int    dxctl_reg_dqsgdly_demux_gated_0  : 1  ; /* [15] */
        unsigned int    dxctl_reg_dqsdly_demux_gated_1   : 1  ; /* [14] */
        unsigned int    dxctl_reg_phy_dqsg_stop_enable   : 1  ; /* [13] */
        unsigned int    dxctl_reg_phy_dqsdly_stop_enable : 1  ; /* [12] */
        unsigned int    reg_resetcon_gated_en_dqs        : 1  ; /* [11] */
        unsigned int    reg_oe_extend1t_en               : 1  ; /* [10] */
        unsigned int    reg_dqsg_tx_2path                : 1  ; /* [9] */
        unsigned int    reg_squeach_en                   : 1  ; /* [8] */
        unsigned int    reg_dqsglat1t_en                 : 1  ; /* [7] */
        unsigned int    reg_sel_halft_gated              : 1  ; /* [6] */
        unsigned int    reg_dynamic_pupden               : 1  ; /* [5] */
        unsigned int    reg_dummypad_use                 : 1  ; /* [4] */
        unsigned int    reg_odten_gated                  : 1  ; /* [3] */
        unsigned int    reg_gds_r1t_sel                  : 1  ; /* [2] */
        unsigned int    bufresetcontn_gated_tdc          : 1  ; /* [1] */
        unsigned int    bufresetcontn_gated_dqsgerror    : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXNMISCCTRL2;

/* Define the union U_DX_DXDEBUGCONFIG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_34                      : 21  ; /* [31:11] */
        unsigned int    dxctl_reg_dbg_gated_n       : 1  ; /* [10] */
        unsigned int    dxctl_reg_dbg_dqsdly_odtpad : 1  ; /* [9] */
        unsigned int    dxctl_reg_dbg_fotest        : 1  ; /* [8] */
        unsigned int    rsv_35                      : 3  ; /* [7:5] */
        unsigned int    dxctl_deskew_regread        : 1  ; /* [4] */
        unsigned int    dxctl_dbg_config            : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXDEBUGCONFIG;

/* Define the union U_DX_DXNDCC */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_36         : 4  ; /* [31:28] */
        unsigned int    dxctl_mclk_dcc : 7  ; /* [27:21] */
        unsigned int    dxctl_dqs_dcc  : 7  ; /* [20:14] */
        unsigned int    dxctl_dqsg_dcc : 7  ; /* [13:7] */
        unsigned int    dxctl_dq_dcc   : 7  ; /* [6:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXNDCC;

/* Define the union U_DX_DXNMISCCTRL3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_37                  : 1  ; /* [31] */
        unsigned int    dxctl_dqsgclk1x_rank1   : 3  ; /* [30:28] */
        unsigned int    dxctl_dqsgclk2x_rank1   : 3  ; /* [27:25] */
        unsigned int    rsv_38                  : 1  ; /* [24] */
        unsigned int    dxctl_sw_margin_code    : 5  ; /* [23:19] */
        unsigned int    rsv_39                  : 7  ; /* [18:12] */
        unsigned int    dxctl_dqsdly_demux_code : 4  ; /* [11:8] */
        unsigned int    dxctl_rxext_dly         : 4  ; /* [7:4] */
        unsigned int    rsv_40                  : 1  ; /* [3] */
        unsigned int    dxctl_dqsg_extdly_dqs   : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXNMISCCTRL3;

/* Define the union U_DX_DXNMISCCTRL4 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_41                        : 2  ; /* [31:30] */
        unsigned int    dxctl_reg_dqsg_toggle_code90  : 6  ; /* [29:24] */
        unsigned int    rsv_42                        : 3  ; /* [23:21] */
        unsigned int    dxctl_reg_1rank_only_en_dqs   : 1  ; /* [20] */
        unsigned int    rsv_43                        : 3  ; /* [19:17] */
        unsigned int    dxctl_reg_clkgated_en_dqs     : 1  ; /* [16] */
        unsigned int    rsv_44                        : 3  ; /* [15:13] */
        unsigned int    dxctl_pack_cfg_rs_passthrough : 1  ; /* [12] */
        unsigned int    rsv_45                        : 3  ; /* [11:9] */
        unsigned int    dxctl_reg_asy_cmd_decode_sel  : 1  ; /* [8] */
        unsigned int    rsv_46                        : 1  ; /* [7] */
        unsigned int    dxctl_reg_rst_n               : 1  ; /* [6] */
        unsigned int    rsv_47                        : 1  ; /* [5] */
        unsigned int    dxctl_reg_dbgmode_byt1_sel    : 1  ; /* [4] */
        unsigned int    dxctl_reg_clkgated_dis        : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXNMISCCTRL4;

/* Define the union U_DX_IOCTL3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_48                    : 15  ; /* [31:17] */
        unsigned int    ioctl_dummy_squeach_pd    : 1  ; /* [16] */
        unsigned int    ioctl_dummy_squeach_clr_b : 1  ; /* [15] */
        unsigned int    ioctl_diffdummy_en        : 1  ; /* [14] */
        unsigned int    ioctl_dummy_pulldn        : 1  ; /* [13] */
        unsigned int    ioctl_dummy_oe            : 1  ; /* [12] */
        unsigned int    dxctl_ioctl_diffdqs_en    : 1  ; /* [11] */
        unsigned int    rsv_49                    : 3  ; /* [10:8] */
        unsigned int    ioctl_dxiopldn_dm         : 1  ; /* [7] */
        unsigned int    ioctl_dxiopldn_dq         : 1  ; /* [6] */
        unsigned int    ioctl_dummy_rx_mode1      : 1  ; /* [5] */
        unsigned int    ioctl_dummy_rx_mode0      : 1  ; /* [4] */
        unsigned int    ioctl_dm_rx_mode1         : 1  ; /* [3] */
        unsigned int    ioctl_dm_rx_mode0         : 1  ; /* [2] */
        unsigned int    ioctl_dqs_rx_mode1        : 1  ; /* [1] */
        unsigned int    ioctl_dqs_rx_mode0        : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_IOCTL3;

/* Define the union U_DX_IOCTL8 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dx_ioctl_tx_duty_en : 16  ; /* [31:16] */
        unsigned int    dx_ioctl_rx_duty_en : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_IOCTL8;

/* Define the union U_DX_DXNDCC1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_50               : 4  ; /* [31:28] */
        unsigned int    dxctl_reg_rx_dcc_dq3 : 7  ; /* [27:21] */
        unsigned int    dxctl_reg_rx_dcc_dq2 : 7  ; /* [20:14] */
        unsigned int    dxctl_reg_rx_dcc_dq1 : 7  ; /* [13:7] */
        unsigned int    dxctl_reg_rx_dcc_dq0 : 7  ; /* [6:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXNDCC1;

/* Define the union U_DX_DXNDCC2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_51               : 4  ; /* [31:28] */
        unsigned int    dxctl_reg_rx_dcc_dq7 : 7  ; /* [27:21] */
        unsigned int    dxctl_reg_rx_dcc_dq6 : 7  ; /* [20:14] */
        unsigned int    dxctl_reg_rx_dcc_dq5 : 7  ; /* [13:7] */
        unsigned int    dxctl_reg_rx_dcc_dq4 : 7  ; /* [6:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXNDCC2;

/* Define the union U_DX_DXNDCC3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_52               : 4  ; /* [31:28] */
        unsigned int    dxctl_reg_tx_dcc_dq3 : 7  ; /* [27:21] */
        unsigned int    dxctl_reg_tx_dcc_dq2 : 7  ; /* [20:14] */
        unsigned int    dxctl_reg_tx_dcc_dq1 : 7  ; /* [13:7] */
        unsigned int    dxctl_reg_tx_dcc_dq0 : 7  ; /* [6:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXNDCC3;

/* Define the union U_DX_DXNDCC4 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_53               : 4  ; /* [31:28] */
        unsigned int    dxctl_reg_tx_dcc_dq7 : 7  ; /* [27:21] */
        unsigned int    dxctl_reg_tx_dcc_dq6 : 7  ; /* [20:14] */
        unsigned int    dxctl_reg_tx_dcc_dq5 : 7  ; /* [13:7] */
        unsigned int    dxctl_reg_tx_dcc_dq4 : 7  ; /* [6:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXNDCC4;

/* Define the union U_DX_BYP_CK90_CODE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_54                       : 8  ; /* [31:24] */
        unsigned int    dxctl_dqsg_code_aft          : 4  ; /* [23:20] */
        unsigned int    dxctl_dqsg_code_bef          : 4  ; /* [19:16] */
        unsigned int    rsv_55                       : 6  ; /* [15:10] */
        unsigned int    dxctl_byp_ck90_data_code_dqs : 10  ; /* [9:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_BYP_CK90_CODE;

/* Define the union U_DX_BYP_CK90_CODE_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_56                : 6  ; /* [31:26] */
        unsigned int    dxctl_byp_ck90_to_phy : 10  ; /* [25:16] */
        unsigned int    rsv_57                : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_BYP_CK90_CODE_2;

/* Define the union U_DX_IOCTL9 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dx_ioctl_tx_duty_inc : 16  ; /* [31:16] */
        unsigned int    dx_ioctl_rx_duty_inc : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_IOCTL9;

/* Define the union U_DX_IOCTL10 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dx_ioctl_tx_duty_sel : 16  ; /* [31:16] */
        unsigned int    dx_ioctl_rx_duty_sel : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_IOCTL10;

/* Define the union U_DX_DXCTL_PHASE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_58                  : 10  ; /* [31:22] */
        unsigned int    dxctl_margin_min_limit  : 5  ; /* [21:17] */
        unsigned int    dxctl_margin_max_limit  : 5  ; /* [16:12] */
        unsigned int    dxctl_dec_margin_tap    : 2  ; /* [11:10] */
        unsigned int    dxctl_inc_margin_tap    : 2  ; /* [9:8] */
        unsigned int    rsv_59                  : 6  ; /* [7:2] */
        unsigned int    dx_half_phase_sel       : 1  ; /* [1] */
        unsigned int    dx_half_phase_sel_rank1 : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXCTL_PHASE;

/* Define the union U_DX_RESERVED_3RD */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    reg_reserve_3rd : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_RESERVED_3RD;

/* Define the union U_DX_DUMMY_IOCTL_DUTY */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_60                  : 20  ; /* [31:12] */
        unsigned int    dummy_ioctl_tx_duty_en  : 2  ; /* [11:10] */
        unsigned int    dummy_ioctl_tx_duty_inc : 2  ; /* [9:8] */
        unsigned int    dummy_ioctl_tx_duty_sel : 2  ; /* [7:6] */
        unsigned int    dummy_ioctl_rx_duty_en  : 2  ; /* [5:4] */
        unsigned int    dummy_ioctl_rx_duty_inc : 2  ; /* [3:2] */
        unsigned int    dummy_ioctl_rx_duty_sel : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DUMMY_IOCTL_DUTY;

/* Define the union U_DX_DXCTL_MISCCTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_61                            : 1  ; /* [31] */
        unsigned int    dxctl_margin_code                 : 5  ; /* [30:26] */
        unsigned int    dxctl_margin_track_clr            : 1  ; /* [25] */
        unsigned int    dxctl_margin_dbg_code             : 9  ; /* [24:16] */
        unsigned int    dxctl_margin_dbg_sel              : 7  ; /* [15:9] */
        unsigned int    dxctl_reg_dbgmode_sel             : 5  ; /* [8:4] */
        unsigned int    dxctl_reg_rdvref_ranksel_en_dqs   : 2  ; /* [3:2] */
        unsigned int    dxctl_reg_rdvref_ranksel_mode_dqs : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXCTL_MISCCTRL;

/* Define the union U_DX_DXRSVD1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dxrsvdreg1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXRSVD1;

/* Define the union U_DX_DXRSVD2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dxrsvdreg2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DX_DXRSVD2;


//==============================================================================
/* Define the global struct */
typedef struct
{
    volatile U_DX_DXPHYCTRL        DX_DXPHYCTRL          ; /* 200 */
    volatile U_DX_IOCTL            DX_IOCTL              ; /* 204 */
    volatile U_DX_DQSSEL           DX_DQSSEL             ; /* 208 */
    volatile U_DX_DXNCKCTRL        DX_DXNCKCTRL          ; /* 20C */
    volatile U_DX_PHYPLLCTRL_DX    DX_PHYPLLCTRL_DX      ; /* 210 */
    volatile U_DX_PHYCTRL2         DX_PHYCTRL2           ; /* 214 */
    volatile U_DX_IOCTL1           DX_IOCTL1             ; /* 218 */
    volatile U_DX_IOCTL2           DX_IOCTL2             ; /* 21C */
    volatile U_DX_PHYPLLCTRL_DX2   DX_PHYPLLCTRL_DX2     ; /* 220 */
    volatile U_DX_PHYPLLCTRL_DX3   DX_PHYPLLCTRL_DX3     ; /* 224 */
    volatile U_DX_IOCTL6           DX_IOCTL6             ; /* 228 */
    volatile U_DX_DXNCLKBDL        DX_DXNCLKBDL          ; /* 230 */
    volatile U_DX_DXNDCC5          DX_DXNDCC5[2]         ; /* 22C */
    volatile U_DX_PHYCTRL0         DX_PHYCTRL0[2]        ; /* 234 */
    volatile U_DX_DXNMISCCTRL0     DX_DXNMISCCTRL0[2]    ; /* 238 */
    volatile U_DX_IOCTL7           DX_IOCTL7             ; /* 240 */
    volatile U_DX_DXNMISCCTRL1     DX_DXNMISCCTRL1[2]    ; /* 264 */
    volatile U_DX_DXDEBUG0         DX_DXDEBUG0[2]        ; /* 23C */
    volatile U_DX_DXPHYRSVD        DX_DXPHYRSVD[2]       ; /* 244 */
    volatile U_DX_DXNMISCCTRL2     DX_DXNMISCCTRL2[2]    ; /* 248 */
    volatile U_DX_DXDEBUGCONFIG    DX_DXDEBUGCONFIG[2]   ; /* 24C */
    volatile U_DX_DXNDCC           DX_DXNDCC[2]          ; /* 250 */
    volatile U_DX_DXNMISCCTRL3     DX_DXNMISCCTRL3[2]    ; /* 254 */
    volatile U_DX_DXNMISCCTRL4     DX_DXNMISCCTRL4[2]    ; /* 258 */
    volatile U_DX_IOCTL3           DX_IOCTL3[2]          ; /* 25C */
    volatile U_DX_IOCTL8           DX_IOCTL8             ; /* 260 */
    volatile U_DX_DXNDCC1          DX_DXNDCC1[2]         ; /* 268 */
    volatile U_DX_DXNDCC2          DX_DXNDCC2[2]         ; /* 26C */
    volatile U_DX_DXNDCC3          DX_DXNDCC3[2]         ; /* 270 */
    volatile U_DX_DXNDCC4          DX_DXNDCC4[2]         ; /* 274 */
    volatile U_DX_BYP_CK90_CODE    DX_BYP_CK90_CODE[2]   ; /* 278 */
    volatile U_DX_BYP_CK90_CODE_2  DX_BYP_CK90_CODE_2[2] ; /* 27C */
    volatile U_DX_IOCTL9           DX_IOCTL9             ; /* 280 */
    volatile U_DX_IOCTL10          DX_IOCTL10            ; /* 284 */
    volatile U_DX_DXCTL_PHASE      DX_DXCTL_PHASE        ; /* 288 */
    volatile U_DX_RESERVED_3RD     DX_RESERVED_3RD       ; /* 28C */
    volatile U_DX_DUMMY_IOCTL_DUTY DX_DUMMY_IOCTL_DUTY   ; /* 290 */
    volatile U_DX_DXCTL_MISCCTRL   DX_DXCTL_MISCCTRL     ; /* 294 */
    volatile U_DX_DXRSVD1          DX_DXRSVD1            ; /* 298 */
    volatile U_DX_DXRSVD2          DX_DXRSVD2            ; /* 29C */

} S_hiddrphy_dx_static_reg_0_REGS_TYPE;

/* Declare the struct pointor of the module hiddrphy_dx_static_reg_0 */
extern volatile S_hiddrphy_dx_static_reg_0_REGS_TYPE *gophiddrphy_dx_static_reg_0AllReg;

/* Declare the functions that set the member value */
int iSetDX_DXPHYCTRL_dxctl_tdc_offset_code_h(unsigned int udxctl_tdc_offset_code_h);
int iSetDX_DXPHYCTRL_dxctl_tdc_offset_code_v(unsigned int udxctl_tdc_offset_code_v);
int iSetDX_DXPHYCTRL_dxctl_pll_lt(unsigned int udxctl_pll_lt);
int iSetDX_DXPHYCTRL_dxctl_margin_cal_rank0_en(unsigned int udxctl_margin_cal_rank0_en);
int iSetDX_DXPHYCTRL_dxctl_pll_sp(unsigned int udxctl_pll_sp);
int iSetDX_DXPHYCTRL_dxctl_pll_cpi(unsigned int udxctl_pll_cpi);
int iSetDX_DXPHYCTRL_dxctl_pll_init(unsigned int udxctl_pll_init);
int iSetDX_DXPHYCTRL_dxctl_pll_testen(unsigned int udxctl_pll_testen);
int iSetDX_IOCTL_dqs_ioctl_odtsel(unsigned int udqs_ioctl_odtsel);
int iSetDX_IOCTL_dx_ioctl_odtsel(unsigned int udx_ioctl_odtsel);
int iSetDX_IOCTL_dxctl_ioctl_pe(unsigned int udxctl_ioctl_pe);
int iSetDX_IOCTL_dxctl_ioctl_hs(unsigned int udxctl_ioctl_hs);
int iSetDX_IOCTL_top_ioctl_odt_oe(unsigned int utop_ioctl_odt_oe);
int iSetDX_IOCTL_dxctl_ioctl_dxiopldn(unsigned int udxctl_ioctl_dxiopldn);
int iSetDX_DQSSEL_reg_dbg_byt0_evntmt_dq47_sel(unsigned int ureg_dbg_byt0_evntmt_dq47_sel);
int iSetDX_DQSSEL_dxctl_dmswap_sel(unsigned int udxctl_dmswap_sel);
int iSetDX_DQSSEL_dxctl_dqswap_sel(unsigned int udxctl_dqswap_sel);
int iSetDX_DXNCKCTRL_dxctl_rg_ck12p(unsigned int udxctl_rg_ck12p);
int iSetDX_DXNCKCTRL_dxctl_regcm2(unsigned int udxctl_regcm2);
int iSetDX_DXNCKCTRL_dxctl_ck11p_dramclk(unsigned int udxctl_ck11p_dramclk);
int iSetDX_DXNCKCTRL_dxctl_ck10p_cmd2t(unsigned int udxctl_ck10p_cmd2t);
int iSetDX_DXNCKCTRL_dxctl_ck9p_cmd1t(unsigned int udxctl_ck9p_cmd1t);
int iSetDX_DXNCKCTRL_dxctl_ck0p_mclk(unsigned int udxctl_ck0p_mclk);
int iSetDX_PHYPLLCTRL_DX_dxctl_pll_lock(unsigned int udxctl_pll_lock);
int iSetDX_PHYPLLCTRL_DX_dxctl_pll_test(unsigned int udxctl_pll_test);
int iSetDX_PHYCTRL2_dxctl_rx_ppfifo_ptr_en(unsigned int udxctl_rx_ppfifo_ptr_en);
int iSetDX_PHYCTRL2_wfifo_dxctl_passthrough(unsigned int uwfifo_dxctl_passthrough);
int iSetDX_PHYCTRL2_wfifo_dxctl_gcken(unsigned int uwfifo_dxctl_gcken);
int iSetDX_PHYCTRL2_dxctl_reg_phy_wdata_ranksw(unsigned int udxctl_reg_phy_wdata_ranksw);
int iSetDX_PHYCTRL2_dxctl_ppfifo_ptr_en(unsigned int udxctl_ppfifo_ptr_en);
int iSetDX_PHYCTRL2_dxctl_reg_rdffsel_2rank_en(unsigned int udxctl_reg_rdffsel_2rank_en);
int iSetDX_PHYCTRL2_dxctl_reg_wfifo_mode(unsigned int udxctl_reg_wfifo_mode);
int iSetDX_PHYCTRL2_margin_cal_gate_en(unsigned int umargin_cal_gate_en);
int iSetDX_PHYCTRL2_dxctl_reg_sel_pos_rx(unsigned int udxctl_reg_sel_pos_rx);
int iSetDX_PHYCTRL2_phy_type(unsigned int uphy_type);
int iSetDX_PHYCTRL2_lpddr4_mode(unsigned int ulpddr4_mode);
int iSetDX_PHYCTRL2_reg_evntmt_en_cmd(unsigned int ureg_evntmt_en_cmd);
int iSetDX_PHYCTRL2_reg_evntmt_sel_cnt_cmd(unsigned int ureg_evntmt_sel_cnt_cmd);
int iSetDX_PHYCTRL2_reg_evntmt_sel_regread_cmd(unsigned int ureg_evntmt_sel_regread_cmd);
int iSetDX_PHYCTRL2_reg_evntmt_tstmode_cmd(unsigned int ureg_evntmt_tstmode_cmd);
int iSetDX_PHYCTRL2_reg_evntmt_edin_dq47_sel(unsigned int ureg_evntmt_edin_dq47_sel);
int iSetDX_PHYCTRL2_reg_evntmt_edin_dq03_sel(unsigned int ureg_evntmt_edin_dq03_sel);
int iSetDX_PHYCTRL2_dxctl_reg_dvalid_selfgen_en(unsigned int udxctl_reg_dvalid_selfgen_en);
int iSetDX_PHYCTRL2_ut_mode(unsigned int uut_mode);
int iSetDX_PHYCTRL2_reg_hs_phy_debug_ck_duty(unsigned int ureg_hs_phy_debug_ck_duty);
int iSetDX_IOCTL1_dxctl_ioctl_odt_iopldn(unsigned int udxctl_ioctl_odt_iopldn);
int iSetDX_IOCTL1_dxctl_odt_ioctl_ronsel(unsigned int udxctl_odt_ioctl_ronsel);
int iSetDX_IOCTL1_dxctl_ioctl_squeach_pd(unsigned int udxctl_ioctl_squeach_pd);
int iSetDX_IOCTL1_dxctl_ioctl_genvref_pd(unsigned int udxctl_ioctl_genvref_pd);
int iSetDX_IOCTL1_dxctl_odt_ioctl_rdsel_n(unsigned int udxctl_odt_ioctl_rdsel_n);
int iSetDX_IOCTL1_dxctl_odt_ioctl_rdsel_p(unsigned int udxctl_odt_ioctl_rdsel_p);
int iSetDX_IOCTL1_dxctl_ioctl_genvref_range_2(unsigned int udxctl_ioctl_genvref_range_2);
int iSetDX_IOCTL2_ioctl_dq_rx_mode1(unsigned int uioctl_dq_rx_mode1);
int iSetDX_IOCTL2_ioctl_dq_rx_mode0(unsigned int uioctl_dq_rx_mode0);
int iSetDX_IOCTL2_dq_vref_sel0(unsigned int udq_vref_sel0);
int iSetDX_IOCTL2_dq_vref_sel1(unsigned int udq_vref_sel1);
int iSetDX_IOCTL2_dxctl_ioctl_genvref_refsel_2(unsigned int udxctl_ioctl_genvref_refsel_2);
int iSetDX_IOCTL2_dxctl_ioctl_genvref_refsel_1(unsigned int udxctl_ioctl_genvref_refsel_1);
int iSetDX_IOCTL2_dxctl_ioctl_genvref_refsel_0(unsigned int udxctl_ioctl_genvref_refsel_0);
int iSetDX_IOCTL2_dxctl_ioctl_genvref_range_1(unsigned int udxctl_ioctl_genvref_range_1);
int iSetDX_IOCTL2_dxctl_ioctl_genvref_range_0(unsigned int udxctl_ioctl_genvref_range_0);
int iSetDX_PHYPLLCTRL_DX2_dxctl_pll_lockin(unsigned int udxctl_pll_lockin);
int iSetDX_PHYPLLCTRL_DX2_dxctl__pll_fopetestref(unsigned int udxctl__pll_fopetestref);
int iSetDX_PHYPLLCTRL_DX2_dxctl__pll_fopetestfb(unsigned int udxctl__pll_fopetestfb);
int iSetDX_PHYPLLCTRL_DX2_dxctl__pll_lockt_sel(unsigned int udxctl__pll_lockt_sel);
int iSetDX_PHYPLLCTRL_DX2_dxctl__pll_initsel(unsigned int udxctl__pll_initsel);
int iSetDX_PHYPLLCTRL_DX2_dxctl__pll_en_cal(unsigned int udxctl__pll_en_cal);
int iSetDX_PHYPLLCTRL_DX2_dxctl__pll_enphsel(unsigned int udxctl__pll_enphsel);
int iSetDX_PHYPLLCTRL_DX2_dxctl__pll_bp_refvco(unsigned int udxctl__pll_bp_refvco);
int iSetDX_PHYPLLCTRL_DX2_dxctl__pll_bp_refpfd(unsigned int udxctl__pll_bp_refpfd);
int iSetDX_PHYPLLCTRL_DX3_dxctl_phazmeter_status(unsigned int udxctl_phazmeter_status);
int iSetDX_PHYPLLCTRL_DX3_dxctl_phazmeter_in(unsigned int udxctl_phazmeter_in);
int iSetDX_IOCTL6_dummy_ioctl_ronselp(unsigned int udummy_ioctl_ronselp);
int iSetDX_IOCTL6_dummy_ioctl_ronseln(unsigned int udummy_ioctl_ronseln);
int iSetDX_IOCTL6_dqs_ioctl_ronbselp(unsigned int udqs_ioctl_ronbselp);
int iSetDX_IOCTL6_dqs_ioctl_ronbseln(unsigned int udqs_ioctl_ronbseln);
int iSetDX_IOCTL6_dx_ioctl_pre_em(unsigned int udx_ioctl_pre_em);
int iSetDX_IOCTL6_dx_ioctl_lp4x_en(unsigned int udx_ioctl_lp4x_en);
int iSetDX_IOCTL6_dqs_ioctl_pre_em(unsigned int udqs_ioctl_pre_em);
int iSetDX_IOCTL6_dqs_ioctl_lp4x_en(unsigned int udqs_ioctl_lp4x_en);
int iSetDX_IOCTL6_dx_ioctl_ronseln(unsigned int udx_ioctl_ronseln);
int iSetDX_IOCTL6_dx_ioctl_ronselp(unsigned int udx_ioctl_ronselp);
int iSetDX_IOCTL6_dqs_ioctl_ronseln(unsigned int udqs_ioctl_ronseln);
int iSetDX_IOCTL6_dqs_ioctl_ronselp(unsigned int udqs_ioctl_ronselp);
int iSetDX_DXNCLKBDL_dxctl_refclk_bdl(unsigned int udxctl_refclk_bdl);
int iSetDX_DXNCLKBDL_dxctl_fbclk_bdl(unsigned int udxctl_fbclk_bdl);
int iSetDX_DXNDCC5_dxctl_reg_tx_dcc_dqs(unsigned int udxctl_reg_tx_dcc_dqs);
int iSetDX_DXNDCC5_dxctl_reg_tx_dcc_dm(unsigned int udxctl_reg_tx_dcc_dm);
int iSetDX_DXNDCC5_dxctl_reg_rx_dcc_dm(unsigned int udxctl_reg_rx_dcc_dm);
int iSetDX_PHYCTRL0_reg_hs_phy_debug_duty(unsigned int ureg_hs_phy_debug_duty);
int iSetDX_PHYCTRL0_reg_hs_phy_debug(unsigned int ureg_hs_phy_debug);
int iSetDX_PHYCTRL0_reg_sel_dqsgated_la_2nd_dqs(unsigned int ureg_sel_dqsgated_la_2nd_dqs);
int iSetDX_PHYCTRL0_reg_rxmargin_inc_en_dqs(unsigned int ureg_rxmargin_inc_en_dqs);
int iSetDX_PHYCTRL0_reg_rxmargin_dec_en_dqs(unsigned int ureg_rxmargin_dec_en_dqs);
int iSetDX_PHYCTRL0_reg_rdqm_en_dqs(unsigned int ureg_rdqm_en_dqs);
int iSetDX_PHYCTRL0_reg_margin_2rank_en_dqs(unsigned int ureg_margin_2rank_en_dqs);
int iSetDX_PHYCTRL0_reg_wdqsbdl_2rank_en_dqs(unsigned int ureg_wdqsbdl_2rank_en_dqs);
int iSetDX_PHYCTRL0_reg_tdvalid_vle_dqs(unsigned int ureg_tdvalid_vle_dqs);
int iSetDX_PHYCTRL0_reg_tdvalid_manctl_dqs(unsigned int ureg_tdvalid_manctl_dqs);
int iSetDX_PHYCTRL0_reg_wrank_src_sel_dqs(unsigned int ureg_wrank_src_sel_dqs);
int iSetDX_PHYCTRL0_reg_gatederr_chk_dis_2nd_dqs(unsigned int ureg_gatederr_chk_dis_2nd_dqs);
int iSetDX_PHYCTRL0_reg_gatedla_pasthr_2nd_dqs(unsigned int ureg_gatedla_pasthr_2nd_dqs);
int iSetDX_PHYCTRL0_reg_tx_dqs_dcc_rank1_dqs(unsigned int ureg_tx_dqs_dcc_rank1_dqs);
int iSetDX_PHYCTRL0_reg_lvdqsclk_rank1_sel_dqs(unsigned int ureg_lvdqsclk_rank1_sel_dqs);
int iSetDX_PHYCTRL0_dxctl_sync_ppfifo_ptr(unsigned int udxctl_sync_ppfifo_ptr);
int iSetDX_PHYCTRL0_reg_evntmt_sel_regread_dq03_dqs(unsigned int ureg_evntmt_sel_regread_dq03_dqs);
int iSetDX_PHYCTRL0_reg_evntmt_sel_regread_dq47_dqs(unsigned int ureg_evntmt_sel_regread_dq47_dqs);
int iSetDX_PHYCTRL0_reg_evntmt_regread_dbgen_dqs(unsigned int ureg_evntmt_regread_dbgen_dqs);
int iSetDX_PHYCTRL0_reg_wdqsrank0_pre1t_sel_dqs(unsigned int ureg_wdqsrank0_pre1t_sel_dqs);
int iSetDX_PHYCTRL0_reg_wdqsrank1_pre1t_sel_dqs(unsigned int ureg_wdqsrank1_pre1t_sel_dqs);
int iSetDX_PHYCTRL0_reg_rx_trans_1rken_dqs(unsigned int ureg_rx_trans_1rken_dqs);
int iSetDX_PHYCTRL0_reg_evntmt_en_dqs(unsigned int ureg_evntmt_en_dqs);
int iSetDX_PHYCTRL0_reg_evntmt_sel_cnt_dqs(unsigned int ureg_evntmt_sel_cnt_dqs);
int iSetDX_PHYCTRL0_reg_evntmt_tstmode_dqs(unsigned int ureg_evntmt_tstmode_dqs);
int iSetDX_DXNMISCCTRL0_reg_reserve_dq0dten_dqs(unsigned int ureg_reserve_dq0dten_dqs);
int iSetDX_DXNMISCCTRL0_dxctl_reg_rxfifo_r1t_sel_dqs(unsigned int udxctl_reg_rxfifo_r1t_sel_dqs);
int iSetDX_DXNMISCCTRL0_dxctl_reg_dqsg_extend_2t_dqs(unsigned int udxctl_reg_dqsg_extend_2t_dqs);
int iSetDX_DXNMISCCTRL0_dxctl_reg_dqsg_extend_en_dqs(unsigned int udxctl_reg_dqsg_extend_en_dqs);
int iSetDX_DXNMISCCTRL0_dxctl_reg_dqsg_toggle_en(unsigned int udxctl_reg_dqsg_toggle_en);
int iSetDX_DXNMISCCTRL0_dxctl_ptrgated_en(unsigned int udxctl_ptrgated_en);
int iSetDX_DXNMISCCTRL0_dxctl_reg_wpst_1p5ten(unsigned int udxctl_reg_wpst_1p5ten);
int iSetDX_DXNMISCCTRL0_dxctl_reg_sel_lvdqsclkdiv2(unsigned int udxctl_reg_sel_lvdqsclkdiv2);
int iSetDX_DXNMISCCTRL0_dxctl_bufphyclkdiv2(unsigned int udxctl_bufphyclkdiv2);
int iSetDX_DXNMISCCTRL0_dxctl_lvdqclkdiv2(unsigned int udxctl_lvdqclkdiv2);
int iSetDX_DXNMISCCTRL0_dxctl_dqsgatedla(unsigned int udxctl_dqsgatedla);
int iSetDX_DXNMISCCTRL0_dxctl_rxp_2nd_dm(unsigned int udxctl_rxp_2nd_dm);
int iSetDX_DXNMISCCTRL0_dxctl_rxn_2nd_dm(unsigned int udxctl_rxn_2nd_dm);
int iSetDX_DXNMISCCTRL0_dxctl_dqs_h(unsigned int udxctl_dqs_h);
int iSetDX_DXNMISCCTRL0_dxctl_dqs_l(unsigned int udxctl_dqs_l);
int iSetDX_DXNMISCCTRL0_reg_dqsdly_pri_en(unsigned int ureg_dqsdly_pri_en);
int iSetDX_DXNMISCCTRL0_dxctl_rxp_2nd_dq(unsigned int udxctl_rxp_2nd_dq);
int iSetDX_DXNMISCCTRL0_dxctl_rxn_2nd_dq(unsigned int udxctl_rxn_2nd_dq);
int iSetDX_IOCTL7_dummy_ioctl_ronbseln(unsigned int udummy_ioctl_ronbseln);
int iSetDX_IOCTL7_dummy_ioctl_ronbselp(unsigned int udummy_ioctl_ronbselp);
int iSetDX_IOCTL7_dm_ioctl_tx_duty_en(unsigned int udm_ioctl_tx_duty_en);
int iSetDX_IOCTL7_dm_ioctl_rx_duty_en(unsigned int udm_ioctl_rx_duty_en);
int iSetDX_IOCTL7_dm_ioctl_tx_duty_inc(unsigned int udm_ioctl_tx_duty_inc);
int iSetDX_IOCTL7_dm_ioctl_rx_duty_inc(unsigned int udm_ioctl_rx_duty_inc);
int iSetDX_IOCTL7_dm_ioctl_tx_duty_sel(unsigned int udm_ioctl_tx_duty_sel);
int iSetDX_IOCTL7_dm_ioctl_rx_duty_sel(unsigned int udm_ioctl_rx_duty_sel);
int iSetDX_IOCTL7_dqs_ioctl_tx_duty_en(unsigned int udqs_ioctl_tx_duty_en);
int iSetDX_IOCTL7_dqs_ioctl_rx_duty_en(unsigned int udqs_ioctl_rx_duty_en);
int iSetDX_IOCTL7_dqs_ioctl_tx_duty_inc(unsigned int udqs_ioctl_tx_duty_inc);
int iSetDX_IOCTL7_dqs_ioctl_rx_duty_inc(unsigned int udqs_ioctl_rx_duty_inc);
int iSetDX_IOCTL7_dqs_ioctl_tx_duty_sel(unsigned int udqs_ioctl_tx_duty_sel);
int iSetDX_IOCTL7_dqs_ioctl_rx_duty_sel(unsigned int udqs_ioctl_rx_duty_sel);
int iSetDX_DXNMISCCTRL1_reg_dqsoe_by_ie_dqs(unsigned int ureg_dqsoe_by_ie_dqs);
int iSetDX_DXNMISCCTRL1_reg_dqsoe_by_wren_dqs(unsigned int ureg_dqsoe_by_wren_dqs);
int iSetDX_DXNMISCCTRL1_dxctl_dqclk1x(unsigned int udxctl_dqclk1x);
int iSetDX_DXNMISCCTRL1_dxctl_dqclk2x(unsigned int udxctl_dqclk2x);
int iSetDX_DXNMISCCTRL1_dxctl_dqclk1x_rank1(unsigned int udxctl_dqclk1x_rank1);
int iSetDX_DXNMISCCTRL1_dxctl_dqclk2x_rank1(unsigned int udxctl_dqclk2x_rank1);
int iSetDX_DXNMISCCTRL1_dxctl_dqsgclk1x(unsigned int udxctl_dqsgclk1x);
int iSetDX_DXNMISCCTRL1_dxctl_dqsgclk2x(unsigned int udxctl_dqsgclk2x);
int iSetDX_DXNMISCCTRL1_dxctl_dqsclk1x(unsigned int udxctl_dqsclk1x);
int iSetDX_DXNMISCCTRL1_dxctl_dqsclk2x(unsigned int udxctl_dqsclk2x);
int iSetDX_DXNMISCCTRL1_dxctl_mclk1x(unsigned int udxctl_mclk1x);
int iSetDX_DXNMISCCTRL1_dxctl_mclk2x(unsigned int udxctl_mclk2x);
int iSetDX_DXDEBUG0_dxctl_evntmt_result_dqm2dq7_byt(unsigned int udxctl_evntmt_result_dqm2dq7_byt);
int iSetDX_DXDEBUG0_dxctl_evntmt_result_dqs02dq3_byt(unsigned int udxctl_evntmt_result_dqs02dq3_byt);
int iSetDX_DXDEBUG0_dxctl_evntmt_done_dqm2dq7_byt(unsigned int udxctl_evntmt_done_dqm2dq7_byt);
int iSetDX_DXDEBUG0_dxctl_evntmt_done_dqs02dq3_byt(unsigned int udxctl_evntmt_done_dqs02dq3_byt);
int iSetDX_DXDEBUG0_dxctl_rlresult_gds_dqs(unsigned int udxctl_rlresult_gds_dqs);
int iSetDX_DXDEBUG0_dxdbg_dqs_s0a(unsigned int udxdbg_dqs_s0a);
int iSetDX_DXDEBUG0_dxdbg_dqs_s0b(unsigned int udxdbg_dqs_s0b);
int iSetDX_DXDEBUG0_dxdbg_dqs_s1a(unsigned int udxdbg_dqs_s1a);
int iSetDX_DXDEBUG0_dxdbg_dqs_s1b(unsigned int udxdbg_dqs_s1b);
int iSetDX_DXDEBUG0_dxdbg_dqs_s2a(unsigned int udxdbg_dqs_s2a);
int iSetDX_DXDEBUG0_dxdbg_dqs_s2b(unsigned int udxdbg_dqs_s2b);
int iSetDX_DXDEBUG0_dxdbg_dqs_rdcnt(unsigned int udxdbg_dqs_rdcnt);
int iSetDX_DXDEBUG0_dxdbg_dqs_ca(unsigned int udxdbg_dqs_ca);
int iSetDX_DXDEBUG0_dxdbg_dqs_cb(unsigned int udxdbg_dqs_cb);
int iSetDX_DXPHYRSVD_dxctl_rsvdctrl(unsigned int udxctl_rsvdctrl);
int iSetDX_DXNMISCCTRL2_dxctl_dqsclk1x_rank1(unsigned int udxctl_dqsclk1x_rank1);
int iSetDX_DXNMISCCTRL2_dxctl_reg_post_gateden(unsigned int udxctl_reg_post_gateden);
int iSetDX_DXNMISCCTRL2_dxctl_byp_clk_gated_dis(unsigned int udxctl_byp_clk_gated_dis);
int iSetDX_DXNMISCCTRL2_dxctl_dqsclk2x_rank1(unsigned int udxctl_dqsclk2x_rank1);
int iSetDX_DXNMISCCTRL2_dxctl_reg_sel_combout(unsigned int udxctl_reg_sel_combout);
int iSetDX_DXNMISCCTRL2_dxctl_reg_tspc_sel(unsigned int udxctl_reg_tspc_sel);
int iSetDX_DXNMISCCTRL2_dxctl_reset_n_phyupdate_req(unsigned int udxctl_reset_n_phyupdate_req);
int iSetDX_DXNMISCCTRL2_dxctl_reg_pn_dlyen(unsigned int udxctl_reg_pn_dlyen);
int iSetDX_DXNMISCCTRL2_dxctl_reg_pre_margin_gated_0(unsigned int udxctl_reg_pre_margin_gated_0);
int iSetDX_DXNMISCCTRL2_dxctl_reg_pre_margin_gated_1(unsigned int udxctl_reg_pre_margin_gated_1);
int iSetDX_DXNMISCCTRL2_dxctl_reg_post_margin_gated_0(unsigned int udxctl_reg_post_margin_gated_0);
int iSetDX_DXNMISCCTRL2_dxctl_reg_post_margin_gated_1(unsigned int udxctl_reg_post_margin_gated_1);
int iSetDX_DXNMISCCTRL2_dxctl_reg_dqsgdly_demux_gated_0(unsigned int udxctl_reg_dqsgdly_demux_gated_0);
int iSetDX_DXNMISCCTRL2_dxctl_reg_dqsdly_demux_gated_1(unsigned int udxctl_reg_dqsdly_demux_gated_1);
int iSetDX_DXNMISCCTRL2_dxctl_reg_phy_dqsg_stop_enable(unsigned int udxctl_reg_phy_dqsg_stop_enable);
int iSetDX_DXNMISCCTRL2_dxctl_reg_phy_dqsdly_stop_enable(unsigned int udxctl_reg_phy_dqsdly_stop_enable);
int iSetDX_DXNMISCCTRL2_reg_resetcon_gated_en_dqs(unsigned int ureg_resetcon_gated_en_dqs);
int iSetDX_DXNMISCCTRL2_reg_oe_extend1t_en(unsigned int ureg_oe_extend1t_en);
int iSetDX_DXNMISCCTRL2_reg_dqsg_tx_2path(unsigned int ureg_dqsg_tx_2path);
int iSetDX_DXNMISCCTRL2_reg_squeach_en(unsigned int ureg_squeach_en);
int iSetDX_DXNMISCCTRL2_reg_dqsglat1t_en(unsigned int ureg_dqsglat1t_en);
int iSetDX_DXNMISCCTRL2_reg_sel_halft_gated(unsigned int ureg_sel_halft_gated);
int iSetDX_DXNMISCCTRL2_reg_dynamic_pupden(unsigned int ureg_dynamic_pupden);
int iSetDX_DXNMISCCTRL2_reg_dummypad_use(unsigned int ureg_dummypad_use);
int iSetDX_DXNMISCCTRL2_reg_odten_gated(unsigned int ureg_odten_gated);
int iSetDX_DXNMISCCTRL2_reg_gds_r1t_sel(unsigned int ureg_gds_r1t_sel);
int iSetDX_DXNMISCCTRL2_bufresetcontn_gated_tdc(unsigned int ubufresetcontn_gated_tdc);
int iSetDX_DXNMISCCTRL2_bufresetcontn_gated_dqsgerror(unsigned int ubufresetcontn_gated_dqsgerror);
int iSetDX_DXDEBUGCONFIG_dxctl_reg_dbg_gated_n(unsigned int udxctl_reg_dbg_gated_n);
int iSetDX_DXDEBUGCONFIG_dxctl_reg_dbg_dqsdly_odtpad(unsigned int udxctl_reg_dbg_dqsdly_odtpad);
int iSetDX_DXDEBUGCONFIG_dxctl_reg_dbg_fotest(unsigned int udxctl_reg_dbg_fotest);
int iSetDX_DXDEBUGCONFIG_dxctl_deskew_regread(unsigned int udxctl_deskew_regread);
int iSetDX_DXDEBUGCONFIG_dxctl_dbg_config(unsigned int udxctl_dbg_config);
int iSetDX_DXNDCC_dxctl_mclk_dcc(unsigned int udxctl_mclk_dcc);
int iSetDX_DXNDCC_dxctl_dqs_dcc(unsigned int udxctl_dqs_dcc);
int iSetDX_DXNDCC_dxctl_dqsg_dcc(unsigned int udxctl_dqsg_dcc);
int iSetDX_DXNDCC_dxctl_dq_dcc(unsigned int udxctl_dq_dcc);
int iSetDX_DXNMISCCTRL3_dxctl_dqsgclk1x_rank1(unsigned int udxctl_dqsgclk1x_rank1);
int iSetDX_DXNMISCCTRL3_dxctl_dqsgclk2x_rank1(unsigned int udxctl_dqsgclk2x_rank1);
int iSetDX_DXNMISCCTRL3_dxctl_sw_margin_code(unsigned int udxctl_sw_margin_code);
int iSetDX_DXNMISCCTRL3_dxctl_dqsdly_demux_code(unsigned int udxctl_dqsdly_demux_code);
int iSetDX_DXNMISCCTRL3_dxctl_rxext_dly(unsigned int udxctl_rxext_dly);
int iSetDX_DXNMISCCTRL3_dxctl_dqsg_extdly_dqs(unsigned int udxctl_dqsg_extdly_dqs);
int iSetDX_DXNMISCCTRL4_dxctl_reg_dqsg_toggle_code90(unsigned int udxctl_reg_dqsg_toggle_code90);
int iSetDX_DXNMISCCTRL4_dxctl_reg_1rank_only_en_dqs(unsigned int udxctl_reg_1rank_only_en_dqs);
int iSetDX_DXNMISCCTRL4_dxctl_reg_clkgated_en_dqs(unsigned int udxctl_reg_clkgated_en_dqs);
int iSetDX_DXNMISCCTRL4_dxctl_pack_cfg_rs_passthrough(unsigned int udxctl_pack_cfg_rs_passthrough);
int iSetDX_DXNMISCCTRL4_dxctl_reg_asy_cmd_decode_sel(unsigned int udxctl_reg_asy_cmd_decode_sel);
int iSetDX_DXNMISCCTRL4_dxctl_reg_rst_n(unsigned int udxctl_reg_rst_n);
int iSetDX_DXNMISCCTRL4_dxctl_reg_dbgmode_byt1_sel(unsigned int udxctl_reg_dbgmode_byt1_sel);
int iSetDX_DXNMISCCTRL4_dxctl_reg_clkgated_dis(unsigned int udxctl_reg_clkgated_dis);
int iSetDX_IOCTL3_ioctl_dummy_squeach_pd(unsigned int uioctl_dummy_squeach_pd);
int iSetDX_IOCTL3_ioctl_dummy_squeach_clr_b(unsigned int uioctl_dummy_squeach_clr_b);
int iSetDX_IOCTL3_ioctl_diffdummy_en(unsigned int uioctl_diffdummy_en);
int iSetDX_IOCTL3_ioctl_dummy_pulldn(unsigned int uioctl_dummy_pulldn);
int iSetDX_IOCTL3_ioctl_dummy_oe(unsigned int uioctl_dummy_oe);
int iSetDX_IOCTL3_dxctl_ioctl_diffdqs_en(unsigned int udxctl_ioctl_diffdqs_en);
int iSetDX_IOCTL3_ioctl_dxiopldn_dm(unsigned int uioctl_dxiopldn_dm);
int iSetDX_IOCTL3_ioctl_dxiopldn_dq(unsigned int uioctl_dxiopldn_dq);
int iSetDX_IOCTL3_ioctl_dummy_rx_mode1(unsigned int uioctl_dummy_rx_mode1);
int iSetDX_IOCTL3_ioctl_dummy_rx_mode0(unsigned int uioctl_dummy_rx_mode0);
int iSetDX_IOCTL3_ioctl_dm_rx_mode1(unsigned int uioctl_dm_rx_mode1);
int iSetDX_IOCTL3_ioctl_dm_rx_mode0(unsigned int uioctl_dm_rx_mode0);
int iSetDX_IOCTL3_ioctl_dqs_rx_mode1(unsigned int uioctl_dqs_rx_mode1);
int iSetDX_IOCTL3_ioctl_dqs_rx_mode0(unsigned int uioctl_dqs_rx_mode0);
int iSetDX_IOCTL8_dx_ioctl_tx_duty_en(unsigned int udx_ioctl_tx_duty_en);
int iSetDX_IOCTL8_dx_ioctl_rx_duty_en(unsigned int udx_ioctl_rx_duty_en);
int iSetDX_DXNDCC1_dxctl_reg_rx_dcc_dq3(unsigned int udxctl_reg_rx_dcc_dq3);
int iSetDX_DXNDCC1_dxctl_reg_rx_dcc_dq2(unsigned int udxctl_reg_rx_dcc_dq2);
int iSetDX_DXNDCC1_dxctl_reg_rx_dcc_dq1(unsigned int udxctl_reg_rx_dcc_dq1);
int iSetDX_DXNDCC1_dxctl_reg_rx_dcc_dq0(unsigned int udxctl_reg_rx_dcc_dq0);
int iSetDX_DXNDCC2_dxctl_reg_rx_dcc_dq7(unsigned int udxctl_reg_rx_dcc_dq7);
int iSetDX_DXNDCC2_dxctl_reg_rx_dcc_dq6(unsigned int udxctl_reg_rx_dcc_dq6);
int iSetDX_DXNDCC2_dxctl_reg_rx_dcc_dq5(unsigned int udxctl_reg_rx_dcc_dq5);
int iSetDX_DXNDCC2_dxctl_reg_rx_dcc_dq4(unsigned int udxctl_reg_rx_dcc_dq4);
int iSetDX_DXNDCC3_dxctl_reg_tx_dcc_dq3(unsigned int udxctl_reg_tx_dcc_dq3);
int iSetDX_DXNDCC3_dxctl_reg_tx_dcc_dq2(unsigned int udxctl_reg_tx_dcc_dq2);
int iSetDX_DXNDCC3_dxctl_reg_tx_dcc_dq1(unsigned int udxctl_reg_tx_dcc_dq1);
int iSetDX_DXNDCC3_dxctl_reg_tx_dcc_dq0(unsigned int udxctl_reg_tx_dcc_dq0);
int iSetDX_DXNDCC4_dxctl_reg_tx_dcc_dq7(unsigned int udxctl_reg_tx_dcc_dq7);
int iSetDX_DXNDCC4_dxctl_reg_tx_dcc_dq6(unsigned int udxctl_reg_tx_dcc_dq6);
int iSetDX_DXNDCC4_dxctl_reg_tx_dcc_dq5(unsigned int udxctl_reg_tx_dcc_dq5);
int iSetDX_DXNDCC4_dxctl_reg_tx_dcc_dq4(unsigned int udxctl_reg_tx_dcc_dq4);
int iSetDX_BYP_CK90_CODE_dxctl_dqsg_code_aft(unsigned int udxctl_dqsg_code_aft);
int iSetDX_BYP_CK90_CODE_dxctl_dqsg_code_bef(unsigned int udxctl_dqsg_code_bef);
int iSetDX_BYP_CK90_CODE_dxctl_byp_ck90_data_code_dqs(unsigned int udxctl_byp_ck90_data_code_dqs);
int iSetDX_BYP_CK90_CODE_2_dxctl_byp_ck90_to_phy(unsigned int udxctl_byp_ck90_to_phy);
int iSetDX_IOCTL9_dx_ioctl_tx_duty_inc(unsigned int udx_ioctl_tx_duty_inc);
int iSetDX_IOCTL9_dx_ioctl_rx_duty_inc(unsigned int udx_ioctl_rx_duty_inc);
int iSetDX_IOCTL10_dx_ioctl_tx_duty_sel(unsigned int udx_ioctl_tx_duty_sel);
int iSetDX_IOCTL10_dx_ioctl_rx_duty_sel(unsigned int udx_ioctl_rx_duty_sel);
int iSetDX_DXCTL_PHASE_dxctl_margin_min_limit(unsigned int udxctl_margin_min_limit);
int iSetDX_DXCTL_PHASE_dxctl_margin_max_limit(unsigned int udxctl_margin_max_limit);
int iSetDX_DXCTL_PHASE_dxctl_dec_margin_tap(unsigned int udxctl_dec_margin_tap);
int iSetDX_DXCTL_PHASE_dxctl_inc_margin_tap(unsigned int udxctl_inc_margin_tap);
int iSetDX_DXCTL_PHASE_dx_half_phase_sel(unsigned int udx_half_phase_sel);
int iSetDX_DXCTL_PHASE_dx_half_phase_sel_rank1(unsigned int udx_half_phase_sel_rank1);
int iSetDX_RESERVED_3RD_reg_reserve_3rd(unsigned int ureg_reserve_3rd);
int iSetDX_DUMMY_IOCTL_DUTY_dummy_ioctl_tx_duty_en(unsigned int udummy_ioctl_tx_duty_en);
int iSetDX_DUMMY_IOCTL_DUTY_dummy_ioctl_tx_duty_inc(unsigned int udummy_ioctl_tx_duty_inc);
int iSetDX_DUMMY_IOCTL_DUTY_dummy_ioctl_tx_duty_sel(unsigned int udummy_ioctl_tx_duty_sel);
int iSetDX_DUMMY_IOCTL_DUTY_dummy_ioctl_rx_duty_en(unsigned int udummy_ioctl_rx_duty_en);
int iSetDX_DUMMY_IOCTL_DUTY_dummy_ioctl_rx_duty_inc(unsigned int udummy_ioctl_rx_duty_inc);
int iSetDX_DUMMY_IOCTL_DUTY_dummy_ioctl_rx_duty_sel(unsigned int udummy_ioctl_rx_duty_sel);
int iSetDX_DXCTL_MISCCTRL_dxctl_margin_code(unsigned int udxctl_margin_code);
int iSetDX_DXCTL_MISCCTRL_dxctl_margin_track_clr(unsigned int udxctl_margin_track_clr);
int iSetDX_DXCTL_MISCCTRL_dxctl_margin_dbg_code(unsigned int udxctl_margin_dbg_code);
int iSetDX_DXCTL_MISCCTRL_dxctl_margin_dbg_sel(unsigned int udxctl_margin_dbg_sel);
int iSetDX_DXCTL_MISCCTRL_dxctl_reg_dbgmode_sel(unsigned int udxctl_reg_dbgmode_sel);
int iSetDX_DXCTL_MISCCTRL_dxctl_reg_rdvref_ranksel_en_dqs(unsigned int udxctl_reg_rdvref_ranksel_en_dqs);
int iSetDX_DXCTL_MISCCTRL_dxctl_reg_rdvref_ranksel_mode_dqs(unsigned int udxctl_reg_rdvref_ranksel_mode_dqs);
int iSetDX_DXRSVD1_dxrsvdreg1(unsigned int udxrsvdreg1);
int iSetDX_DXRSVD2_dxrsvdreg2(unsigned int udxrsvdreg2);

#endif // __HIDDRPHY_DX_STATIC_REG_0_C_UNION_DEFINE_H__
